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黑芝麻智能
Black Sesame Technologies Wudang C1296
The industry's first chip platform to support multi-domain fusion
黑芝麻智能
Product advantages
黑芝麻智能
Hybrid Hardware and Software Architecture Design: Balancing Security, Cost, and Flexibilit
Through the FFI isolated MPU, low-cost implementation of typical cockpit-ADAS integration is achieved. Additionally, with hardware acceleration for the hypervisor, it flexibly meets the needs of more complex and variable scenarios, facilitating the smooth evolution of the automobile's electronic and electrical architecture.
Vehicle Safety Regulations without Compromise
The whole SOC development process, including IP selection, architecture design, production process, and packaging, uses auto-grade standards, ensuring uncompromised safety.
High Performance x Low Power Consumption: Making algorithm Perception Technology More Reliable
Based on built-in automotive-specific high-performance ISP, CV, and NPU, it supports a technology framework centered on camera sensing and algorithm computing, enabling technology to show real intelligence.
Product highlights
黑芝麻智能
Specification
10 Cores High-performance ARM Cortex A78AE Automotive GradeCPU

• 5 times better than perviouse genration of performance

• DCLS supported, ASIL-D

The First High-performance ARM Automotive Grade GPU Mali G78AE

• 20 times better than perviouse genration of performance

• DCLS supported, ASIL-D

High Performance, High Energy-efficient DynamAl NN Engine
(For multiple channels camera access andhigh performance computing scenario usage)

• Hybrid precision 4-bit/8-bit MAC Array

• Overall 80% utilization of convolution layers MAC Array

• Sparse support for storage and acceleration

• Int 8/16-bit, floating 16 bit GEMM and Nonlinear functions acceleration

• Open-source and familized DynamAl NN compiler tools

High Performance Real-time Processing Capability

• Built-in high performance real-time processing computing power to 32KDMIPS (16DMIPS in DCLS)

Optimized Memory System Architecture

• Cache specifications that match high-performance CPU: 512KB L2 Cache, 2MB L3 Cache/Cluster

• Built-in 12MB super large SRAM space

• Automotive grade 64bit LPDDR5/LPDDR4X

Automotive Grade NeurallQ ISP Pipeline Enhanced Version

• 12 channels HD camera input

• More than 17MP camera input supported

• 3-exposure HDR, up to 140dB dynamic range

• Offline low-light denoising and LED flash suppression

• Support for RGB-IR Sensor added

• Processing 2.4G pixels per second

High performance HIFI5 DSP

• Latest generation Audio DSP

• Built-in NNE to speed up sound processing algorithms

Computer Vision Processing Hardware Accelerator

• 5 cores high performance vision DSP

• CV Hardware acceleration

• H.264/H.265 video encoder and decoder for 4k video

Rich interfaces of Automotive Grade Screen

• Rich interface types: 2xDSI, 2xLVDS, 1x DP/eDP

• Support 4K standard screen and long screen display

• Mutiple screen output supported

Built-in High-speed Switch Acceleration Module

• 2x10 GbE + 2x2.5 GE Line speed forwarding capability

• CAN-ETH high-speed swiching capability

Separate PCIe 4.0 High-speed Port

• Support 2x2 Lane and 1x4 Lane configuration

• Ethernet port nontaken

Rich Peripheral Interfaces, Fully Compatible with New and Old Auto-grade regulations

• More than 20 CAN-FD supported

• More than 6 LIN interfaces supported

• Support FlesRay interface

• 2xUSB3.1 device

• UFS3.1

• UART、SPI、I2C、I3C、I2S、TDM、GPIO

7nm Automotive Process
Soft and Hard Cross-domain Architecture and System Design

• Hard isolated MPU unit, low-cost implementation of cross-domain typical system solutions

• Combined with VMS, it flexibly meets the requirements of complex cross-domain scenarios

Package

• FCBGA 31*31 mm, 0.8 mm pitch

• Be compatible with C1200 family Pin2Pin

Operating Conditions

• Environment -40°C~105°C

Function Safety and Information Security

• Verified bylS026262 ASIL-B and AEC-0100 Grade-2 standard

• CPU, GPU with dual-cores lockstep supported

• Real time security monitoring and inspection

• Embedded safety guard mechanism involving ECC, Parity

• EVITA-Full and OSCCA

• Secure booting

• OTP on chip for Private-keystorage and life-cycle management

• Multiple independent hardware encryption and decryption engines, dedicated hardware acceleration engines for secure communication

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